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d a t a sh eet product speci?cation file under integrated circuits, ic22 1999 jul 01 integrated circuits saa7113h 9-bit video input processor
1999 jul 01 2 philips semiconductors product speci?cation 9-bit video input processor saa7113h contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 analog input processing 8.2 analog control circuits 8.3 chrominance processing 8.4 luminance processing 8.5 synchronization 8.6 clock generation circuit 8.7 power-on reset and ce input 8.8 multi-standard vbi data slicer 8.9 vbi-raw data bypass 8.10 digital output port vpo7 to vpo0 8.11 rtco output 8.12 rts0, rts1 terminals 9 boundary scan test 9.1 initialization of boundary scan circuit 9.2 device identification codes 10 limiting values 11 thermal characteristics 12 characteristics 13 timing diagrams 14 application information 15 i 2 c-bus description 15.1 i 2 c-bus format 15.2 i 2 c-bus detail 16 i 2 c-bus start set-up 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 definitions 20 life support applications 21 purchase of philips i 2 c components
1999 jul 01 3 philips semiconductors product speci?cation 9-bit video input processor saa7113h 1 features four analog inputs, internal analog source selectors, e.g. 4 cvbs or 2 y/c or (1 y/c and 2 cvbs) two analog preprocessing channels in differential cmos style for best s/n-performance fully programmable static gain or automatic gain control for the selected cvbs or y/c channel switchable white peak control two built-in analog anti-aliasing filters two 9-bit video cmos analog-to-digital converters (adcs), digitized cvbs or y/c-signals are available on the vpo-port via i 2 c-bus control on-chip clock generator line-locked system clock frequencies digital pll for horizontal sync processing and clock generation, horizontal and vertical sync detection requires only one crystal (24.576 mhz) for all standards automatic detection of 50 and 60 hz field frequency, and automatic switching between pal and ntsc standards luminance and chrominance signal processing for pal bghi, pal n, combination pal n, pal m, ntsc m, ntsc n, ntsc 4.43, ntsc-japan and secam user programmable luminance peaking or aperture correction cross-colour reduction for ntsc by chrominance comb filtering pal delay line for correcting pal phase errors brightness contrast saturation (bcs) and hue control on-chip real-time status information output (rtco) two multi functional real-time output pins controlled by i 2 c-bus multi-standard vbi-data slicer decoding world standard teletext (wst), north-american broadcast text system (nabts), closed caption, wide screen signalling (wss), video programming system (vps), vertical interval time code (vitc) variants (ebu/smpte) etc. standard itu 656 yu v4:2:2 format (8-bit) on vpo output bus enhanced itu 656 output format on vpo output bus containing: C active video C raw cvbs data for intercast applications (27 mhz data rate) C decoded vbi data boundary scan test circuit complies with the ieee std. 1149.b1 - 1994 (id-cod e = 1 7113 02b) i 2 c-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s) low power (<0.5 w), low voltage (3.3 v), small package (qfp44) power saving mode by chip enable input 5 v tolerant digital i/o ports detection of copy protected input signals according to the macrovision standard. can be used to prevent unauthorized recording of pay-tv or video tape signals. 2 applications notebook (low power consumption) pcmcia card application agp based graphics cards image processing video phone applications intercast and pc teletext applications security applications.
1999 jul 01 4 philips semiconductors product speci?cation 9-bit video input processor saa7113h 3 general description the 9-bit video input processor is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and adc, an automatic clamp and gain control, a clock generation circuit (cgc), a digital multi-standard decoder (pal bghi, pal m, pal n, combination pal n, ntsc m, ntsc-japan, ntsc n and secam), a brightness, contrast and saturation control circuit, a multi-standard vbi data slicer and a 27 mhz vbi data bypass; see fig.1. the pure 3.3 v (5 v compatible) cmos circuit saa7113h, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. the decoder is based on the principle of line-locked clock decoding and is able to decode the colour of pal, secam and ntsc signals into ccir-601 compatible colour component values. the saa7113h accepts as analog inputs cvbs or s-video (y/c) from tv or vtr sources. the circuit is i 2 c-bus controlled. the integrated high performance multi-standard data slicer supports several vbi data standards: teletext [wst (world standard teletext), ccst (chinese teletext)] (625 lines) teletext [us-wst, nabts (north-american broadcast text system) and moji (japanese teletext)] (525 lines) closed caption [europe, us (line 21)] wide screen signalling (wss) video programming signal (vps) time codes (vitc ebu/smpte) high-speed vbi data bypass for intercast application. 4 quick reference data 5 ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.1 3.3 3.5 v t amb operating ambient temperature 0 25 70 c p a+d analog and digital power dissipation - 0.4 - w type number package name description version saa7113h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
1999 jul 01 5 philips semiconductors product speci?cation 9-bit video input processor saa7113h 6 block diagram fig.1 block diagram. handbook, full pagewidth multi-standard data slicer mhb323 saa7113h i 2 c-bus interface output formatter i 2 c-bus control vbi data bypass upsampling filter chrominance circuit and brightness contrast saturation control luminance circuit test control block for boundary scan test and scan test synchronization circuit bypass 38 tdi 37 tck 39 tms 8 trst 36 tdo analog processing control 6 agnd 41 v ssa2 42 v dda2 2 v ssa1 3 v dda1 analog processing and analog-to- digital conversion 4 ai11 5 ai1d 7 ai12 43 ai21 44 ai2d 1 ai22 9 aout clock generation circuit power-on control clocks 32 xtali 23 uv y/cvbs c/cvbs y y y con ad2 ad1 sda 24 scl 31 xtal 17 lfco llc 12 to 15, 19 to 22 vpo7 to vpo0 40 ce 11 v dda0 10 v ssa0 v ddde2 34 35 v ssde2 v ddda 33 30 v ssda v dddi 29 28 v ssdi v ddde1 18 16 v ssde1 25 rtco 27 rts1 26 rts0
1999 jul 01 6 philips semiconductors product speci?cation 9-bit video input processor saa7113h 7 pinning symbol pin i/o/p description ai22 1 i analog input 22 v ssa1 2 p ground for analog supply voltage channel 1 v dda1 3 p positive supply voltage for analog channel 1 (+3.3 v) ai11 4 i analog input 11 ai1d 5 i differential analog input for ai11 and ai12; has to be connected to ground via a capacitor; see application diagram of fig.31 agnd 6 p analog signal ground connection ai12 7 i analog input 12 trst 8 i test reset input (active low), for boundary scan test; notes 1, 2 and 3 aout 9 o analog test output; for testing the analog input channels, 75 w termination possible v dda0 10 p positive supply voltage (+3.3 v) for internal clock generation circuit (cgc) v ssa0 11 p ground for internal clock generation circuit vpo7 to vpo4 12 to 15 o digital vpo-bus output signal; higher bits of the 8-bit output bus. the output data types of the vpo-bus are controlled via i 2 c-bus registers lcr2 to lcr24; see table 4. if i 2 c-bus bit vipb = 1, the higher bits of the digitized input signal are connected to these outputs, con?gured by the i 2 c-bus control signals mode3 to mode0 v ssde1 16 p ground 1 or digital supply voltage input e (external pad supply) llc 17 o line-locked system clock output (27 mhz) v ddde1 18 p digital supply voltage e1 (external pad supply 1; +3.3 v) vpo3 to vpo0 19 to 22 o digital vpo-bus output signal; lower bits of the 8-bit output bus. the output data types of the vpo-bus are controlled via i 2 c-bus registers lcr2 to lcr24; see table 4. if i 2 c-bus bit vipb = 1, the lower bits of the digitized input signal are connected to these outputs, con?gured by the i 2 c-bus control signals mode3 to mode0 sda 23 i/o serial data input/output (i 2 c-bus) 5 v-compatible scl 24 i serial clock input (i 2 c-bus) 5 v-compatible rtco 25 (i/)o real-time control output: contains information about actual system clock frequency, ?eld rate, odd/even sequence, decoder status, subcarrier frequency and phase and pal sequence (see external document rtc functional description , available on request); the rtco pin is enabled via i 2 c-bus bit oert; this pin is also used as an input pin for test purposes and has an internal pull-down resistor; do not connect any pull-up resistor to this pin rts0 26 (i/)o real-time signal output 0: multi functional output, controlled by i 2 c-bus bits rtse03 to rtse00; see table 49. rts0 is strapped during power-on or ce driven reset, de?nes which i 2 c-bus slave address is used; 0 = 48h for write, 49h for read, external pull-down resistor of 3.3 k w is needed; 1 = 4ah for write, 4bh for read, default slave address (default, internal pull-up) rts1 27 i/o real-time signal i/o terminal 1: multi functional output, controlled by i 2 c-bus bit rtse13 to rtse10; see table 50 v ssdi 28 p ground for internal digital core supply v dddi 29 p internal core supply (+3.3 v) v ssda 30 p digital ground for internal crystal oscillator xtal 31 o second terminal of crystal oscillator; not connected if external clock signal is used
1999 jul 01 7 philips semiconductors product speci?cation 9-bit video input processor saa7113h notes 1. for board design without boundary scan implementation connect the trst pin to ground. 2. this pin provides easy initialization of bst circuit. trst can be used to force the test access port (tap) controller to the test_logic_reset state (normal operation) at once. 3. in accordance with the ieee1149.1 standard the pads tdi, tms and trst are input pads with an internal pull-up transistor and tdo is a 3-state output pad. xtali 32 i input terminal for crystal oscillator or connection of external oscillator with cmos compatible square wave clock signal v ddda 33 p digital positive supply voltage for internal crystal oscillator (+3.3 v) v ddde2 34 p digital supply voltage e2 (external pad supply 2; +3.3 v) v ssde2 35 p ground 2 for digital supply voltage input e (external pad supply) tdo 36 o test data output for boundary scan test; note 3 tck 37 i test clock for boundary scan test; note 3 tdi 38 i test data input for boundary scan test; note 3 tms 39 i test mode select input for boundary scan test or scan test; note 3 ce 40 i chip enable, sleep mode with low power consumption if connected to ground (internal pull-up); internal reset sequence is generated when released v ssa2 41 p ground for analog supply voltage channel 2 v dda2 42 p positive supply voltage for analog channel 2 (+3.3 v) ai21 43 i analog input 21 ai2d 44 i differential analog input for ai21 and ai22; has to be connected to ground via a capacitor; see application diagram of fig.31 symbol pin i/o/p description
1999 jul 01 8 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 saa7113h ai12 aout v dda0 v ssa0 ai1d ai11 v dda1 v ssa1 ai22 agnd trst mhb324 vpo7 vpo5 vpo4 llc vpo3 vpo2 vpo1 vpo0 v ddde1 vpo6 v ssde1 tms tdi tck tdo v ddde2 v ssde2 ai2d v dda2 v ssa2 ce ai21 v ddda xtali xtal v ssda v dddi sda scl rts0 rts1 v ssdi rtco
1999 jul 01 9 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8 functional description 8.1 analog input processing the saa7113h offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit cmos adc; see fig.6. 8.2 analog control circuits the anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. the characteristics are shown in fig.3. during the vertical blanking period, gain and clamping control are frozen. fig.3 anti-alias filter. handbook, full pagewidth 6 v (db) - 42 024 68101214 f (mhz) mgd138 - 6 - 12 - 18 - 24 - 30 - 36 0 8.2.1 c lamping the clamp control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and filter the clamping voltage. an internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. the clamping levels for the two adc channels are fixed for luminance (120) and chrominance (256). clamping time in normal use is set with the hcl pulse at the back porch of the video signal. 8.2.2 g ain control the gain control circuit receives (via the i 2 c-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (agc) as part of the analog input control (aico). the agc (automatic gain control for luminance) is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the agc active time is the sync bottom of the video signal. signal (white) peak control limits the gain at signal overshoots. the flow charts (see figs 7 and 8) show more details of the agc. the influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.
1999 jul 01 10 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.4 analog line with clamp (hcl) and gain range (hsy). handbook, halfpage hcl mgl065 hsy analog line blanking tv line 1 60 255 gain clamp fig.5 automatic gain range. handbook, halfpage analog input level controlled adc input level maximum minimum range 9 db 0 db 0 db mhb325 + 3 db - 6 db (1 v (p-p) 18/56 w )
1999 jul 01 11 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... n dbook, full pagewidth mhb326 holdg gafix wpoff gudl0-gudl2 gai20-gai28 gai10-gai18 hlnrs uptcv mode 3 mode 2 mode 1 mode 0 hsy hcl glimb glimt wipa sltca analog control vbsl source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc2 source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc1 vblnk svref cross multiplexer vertical blanking control clamp control gain control anti-alias control mode control fuse (1 : 0) fuse (1 : 0) aosl (1 : 0) agnd 6 chr lum 99 ad1byp ad2byp 9 aout 7 5 4 2 41 1 44 3 42 43 ai22 ai12 ai2d ai1d ai21 ai11 test selector and buffer v dda1 v ssa2 v dda2 v ssa1 fig.6 analog input processing using the saa7113h as differential front-end with 9-bit adc.
1999 jul 01 12 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.7 gain flow chart. x = system variable; y = (iagv - fgvi) > gudl; vblk = vertical blanking pulse; hsy = horizontal sync pulse; agv = actual gain value; fgv = frozen gain value. handbook, full pagewidth analog input amplifier anti-alias filter adc luma/chroma decoder x hsy > 254 > 254 < 1 < 4 > 248 x = 0 x = 1 - 1/llc2 + 1/llc2 - 1/llc2 + / - 0 + 1/f + 1/l gain accumulator (18 bits) actual gain value 9-bit (agv) [ - 6/ + 6 db] x stop hsy y update fgv mhb327 agv gain value 9-bit 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 vblk 1 0 no action 9 9 dac gain holdg
1999 jul 01 13 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.8 clamp and gain flow. wipe = white peak level (254); sbot = sync bottom level (1); cll = clamp level [60 y (128 c)]; hsy = horizontal sync pulse; hcl = horizontal clamp pulse. handbook, full pagewidth 10 + clamp - clamp no clamp 10 10 01 10 mgc647 fast - gain slow + gain + gain - gain hcl hsy adc sbot wipe cll analog input gain -> <- clamp vblk no blanking active 10 8.3 chrominance processing the 9-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator dto1 are applied (0 and 90 phase relationship to the demodulator axis). the frequency is dependent on the present colour standard. the output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (pal, ntsc) or the 0 and 90 fm signals (secam). the colour difference signals are fed to the brightness/contrast/saturation block (bcs), which includes the following five functions: agc (automatic gain control for chrominance pal and ntsc) chrominance amplitude matching (different gain factors for (r - y) and (b - y) to achieve ccir-601 levels c r and c b for all standards) chrominance saturation control luminance contrast and brightness limiting yuv to the values 1 (minimum) and 254 (maximum) to fulfil ccir-601 requirements. the secam-processing contains the following blocks: baseband bell filters to reconstruct the amplitude and phase equalized 0 and 90 fm signals phase demodulator and differentiator (fm-demodulation) de-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (db or dr white carrier values are subtracted from the signal, controlled by the secam switch signal). the burst processing block provides the feedback loop of the chrominance pll and contains: burst gate accumulator colour identification and killer comparison nominal/actual burst amplitude (pal/ntsc standards only)
1999 jul 01 14 philips semiconductors product speci?cation 9-bit video input processor saa7113h loop filter chrominance gain control (pal/ntsc standards only) loop filter chrominance pll (only active for pal/ntsc standards) pal/secam sequence detection, h/2-switch generation increment generation for dto1 with divider to generate stable subcarrier for non-standard signals. the chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the pal standard requirements. for ntsc colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. the comb filter can be switched off if desired. the embedded line delay is also used for secam recombination (cross-over switches). the resulting signals are fed to the variable y-delay compensation and the output interface, which contains the vpo output formatter and the output control logic, see fig.10. fig.9 chrominance filter. transfer characteristics of the chrominance low-pass dependent on chbw[1 : 0] settings. handbook, full pagewidth 2.7 6 0 - 6 - 12 - 18 - 24 - 30 - 36 - 42 - 48 - 54 0 0.54 1.08 1.62 2,16 mgd147 f (mhz) v (db) (1) (2) (3) (4) (4) (1) (3) (2) (1) chbw[1 : 0] = 00. (2) chbw[1 : 0] = 01. (3) chbw[1 : 0] = 10. (4) chbw[1 : 0] = 11.
1999 jul 01 15 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... n dbook, full pagewidth chr lum code ad1byp ad2byp brig cont satn huec dccf f h /2 switch signal mhb328 v ddde1 v ssde1 18 v dddi 29 v ddda 33 v ddde2 34 16 v ssdi 28 v ssda 30 v ssde2 35 25 12, 13, 14, 15, 19, 20, 21, 22 vpo7 to vpo0 quadrature demodulator comb filters secam recombination output formatter and interface burst gate accumulator low-pass reset loop filter subcarrier increment generation and divider subcarrier generation fctc cstd 1 secam processing chbw0 chbw1 cstd 0 incs tck tdi 37 38 power-on control test control block tdo trst 36 8 tms 39 lum y rtco clocks ce y sequential uv signals uv uv vbi data bypass upsampling filter phase demodulator amplitude detector ofts0 ofts1 oeyc oehv vrln vsta (8 : 0) vsto (8 : 0) gpsw (1 : 0) rtse1 (7 : 0) rtse0 (7 : 0) vipb colo level adjustment, brightness, contrast, and saturation control gain control and y-delay compensation data slicer input multi-standard data slicer interfacing multi-standard data slicer fig.10 chrominance circuit, text slicer, vbi-bypass, output formatting, power and test control.
1999 jul 01 16 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8.4 luminance processing the 9-bit luminance signal, a digital cvbs format or a luminance format (s-vhs, hi8), is fed through a switchable prefilter. high frequency components are emphasized to compensate for loss. the following chrominance trap filter (f 0 = 4.43 or 3.58 mhz centre frequency set according to the selected colour standard) eliminates most of the colour carrier signal. it should be bypassed via i 2 c-bit byps (subaddress 09h, bit 7) for s-video (s-vhs, hi8) signals. the high frequency components of the luminance signal can be peaked (control for sharpness improvement via i 2 c-bus subaddress 09h, see table 36) in two band-pass filters with selectable transfer characteristic. this signal is then added to the original (unpeaked) signal. for the resulting frequency characteristics see figs 11 to 18. a switchable amplifier achieves common dc amplification, because the dc gains are different in both chrominance trap modes. the improved luminance signal is fed to the bcs control located in the chrominance processing block, see fig.19. fig.11 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter on, different aperture band-pass centre frequencies. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd139 6 v y (db) - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) (1) 43h. (2) 53h. (3) 63h. (4) 73h.
1999 jul 01 17 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.12 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter on, different aperture factors. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd140 6 - 18 - 6 (1) (2) (3) (4) (4) (3) (2) (1) v y (db) (1) 40h. (2) 41h. (3) 42h. (4) 43h. fig.13 luminance control sa 09h, 4.43 mhz trap/cvbs mode, prefilter off, different aperture band-pass centre frequencies. (1) 03h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd141 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db) (2) 13h. (3) 23h. (4) 33h.
1999 jul 01 18 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.14 luminance control sa 09h, y/c mode, prefilter on, different aperture factors. (1) c0h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd142 6 - 18 - 6 (1) (2) (3) (4) v y (db) (2) c1h. (3) c2h. (4) c3h. fig.15 luminance control sa 09h, y/c mode, prefilter off, different aperture factors. (1) 80h. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd143 6 - 18 - 6 (1) (2) (3) (4) v y (db) (2) 81h. (3) 82h. (4) 83h.
1999 jul 01 19 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.16 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter on, different aperture band-pass centre frequencies. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd144 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db) (1) 43h. (2) 53h. (3) 63h. (4) 73h. fig.17 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter on, different aperture factors. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd145 6 - 18 - 6 (1) (2) (3) (4) (4) (3) (2) (1) v y (db) (1) 40h. (2) 41h. (3) 42h. (4) 43h.
1999 jul 01 20 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.18 luminance control sa 09h, 3.58 mhz trap/cvbs mode, prefilter off, different aperture band-pass centre frequencies. handbook, full pagewidth f y (mhz) 18 - 30 024 8 6 mgd146 6 - 18 - 6 (1) (2) (4) (3) (1) (2) (4) (3) v y (db) (1) 03h. (2) 13h. (3) 23h. (4) 33h.
1999 jul 01 21 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... d book, full pagewidth pref aper0 aper1 vblb bpss0 bpss1 pref vblb copro chrominance trap prefilter prefilter sync sync slicer byps variable band-pass filter macrovision detector lum vblb luminance circuit y matching amplifier phase detector fine phase detector coarse aufd hsb (7 : 0) hss (7 : 0) fsel fidt vnoi0 vnoi1 htc (1 : 0) htc (1 : 0) hpll htc (1 : 0) hlck loop filter 2 discrete time oscillator 2 vertical processor counter xtali xtal ce v dda0 24 23 26 27 i 2 c-bus control dac6 i 2 c-bus interface rts0 sda scl rts1 incs 31 32 11 40 10 17 v ssa0 clocks synchronization circuit mhb329 llc weighting and adding stage line-locked clock generator crystal clock generator clock generation circuit clock circuit fig.19 luminance and sync processing.
1999 jul 01 22 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8.5 synchronization the prefiltered luminance signal is fed to the synchronization stage. its bandwidth is further reduced to 1 mhz in a low-pass filter. the sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop filter to accumulate all phase deviations. internal signals (e.g. hcl and hsy) are generated in accordance with analog front-end requirements. the loop filter signal drives an oscillator to generate the line frequency control signal lfco, see fig.19. the detection of pseudo syncs as part of the macrovision copy protection standard is also done within the synchronization circuit. the result is reported as flag copro within the decoder status byte at subaddress 1fh. 8.6 clock generation circuit the internal cgc generates all clock signals required for the video input processor. the internal signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency [6.75 mhz = 429 f h (50 hz) or 432 f h (60 hz)]. internally the lfco signal is multiplied by a factor of 2 and 4 in the pll circuit (including phase detector, loop filtering, vco and frequency divider) to obtain the output clock signals. the rectangular output clocks have a 50% duty factor. fig.20 block diagram of clock generation circuit. handbook, full pagewidth band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator mhb330 llc2 llc lfco table 1 clock frequencies clock frequency (mhz) xtal 24.576 llc 27 llc2 (internal) 13.5 llc4 (internal) 6.75 llc8 (virtual) 3.375 8.7 power-on reset and ce input a missing clock, insufficient digital or analog v dda0 supply voltages (below 2.8 v) will initiate the reset sequence; all outputs are forced to 3-state (see fig.21). it is possible to force a reset by pulling the chip enable (ce) to ground. after the rising edge of ce and sufficient power supply voltage, the outputs llc and sda return from 3-state to active, while rts0, rts1 and rtco remain in 3-state and have to be activated via i 2 c-bus programming (see table 2).
1999 jul 01 23 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.21 power-on control circuit. ce = chip enable input; xtal = crystal oscillator output; llcint = internal system clock; resint = internal reset; llc = line-locked clock output. handbook, full pagewidth mhb331 128 lcc 896 lcc digital delay some ms 20 to 200 m s pll-delay < 1 ms res (internal reset) llc resint llcint xtal ce poc v dda poc logic analog poc v ddd digital poc delay clock pll ce llc clk0 resint res
1999 jul 01 24 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 2 power-on control sequence internal power-on control sequence pin output status remarks directly after power-on asynchronous reset vpo7 to vpo0, rtco, rts0, rts1, sda and llc are in high-impedance state direct switching to high-impedance for 20 to 200 ms synchronous reset sequence llc and sda become active; vpo7 to vpo0, rtco, rts0 and rts1 are held in high-impedance state internal reset sequence status after power-on control sequence vpo7 to vpo0, rtco, rts0 and rts1 are held in high-impedance state after power-on (reset sequence) a complete i 2 c-bus transmission is required 8.8 multi-standard vbi data slicer the multi-standard data slicer is a vertical blanking interval (vbi) and full field (ff) video data acquisition block. in combination with software modules the slicer acquires most existing formats of broadcast vbi and ff data. the implementation and programming model of the multi-standard vbi data slicer is similar to the text slicer built in the multimedia video data acquisition circuit saa5284 . the circuitry recovers the actual clock phase during the clock-run-in-period, slices the data bits with the selected data rate, and groups them into bytes. the clock frequency, signals source, field frequency and accepted error count must be defined via the i 2 c-bus in subaddress 40h, ac1: bits d7 to d4. several standards can be selected per vbi line. the supported vbi data standards are described in table 3. the programming of the desired standards is done via i 2 c-bus subaddresses 41h to 57h (lcr2[7 : 0] to lcr24[7 : 0]); see detailed description in chapter 8.10. to adjust the slicers processing to the signals source, there are offsets in horizontal and vertical direction available via the i 2 c-bus in subaddresses 5bh (bits 2 to 0), 59h (hoff10 to hoff0) and 5bh (bit 4), 5ah (voff8 to voff0). the formatting of the decoded vbi data is done within the output interface to the vpo-bus. for a detailed description of the sliced data format see table 17. table 3 supported vbi standards standard type data rate (mbits/s) framing code fc window ham check teletext eurowst, ccst 6.9375 27h wst625 always european closed caption 0.500 001 cc625 vps 5 9951h vps wide screen signalling bits 5 1e3c1fh wss us teletext (wst) 5.7272 27h wst525 always us closed caption (line 21) 0.503 001 cc525 teletext 6.9375 programmable general text optional vitc/ebu time codes (europe) 1.8125 programmable vitc625 vitc/smpte time codes (usa) 1.7898 programmable vitc625 us nabts 5.7272 programmable nabts optional moji (japanese) 5.7272 programmable (a7h) japtext japanese format switch (l20/22) 5 programmable
1999 jul 01 25 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8.9 vbi-raw data bypass for a 27 mhz vbi-raw data bypass the digitized cvbs signal is upsampled after ad-conversion. suppressing of the back folded cvbs frequency components after upsampling is achieved by an interpolation filter; see fig.22. handbook, full pagewidth 6 v (db) - 42 - 48 - 54 024 68101214 f (mhz) mgg067 - 6 - 12 - 18 - 24 - 30 - 36 0 fig.22 interpolation filter for the upsampled cvbs signal.
1999 jul 01 26 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8.10 digital output port vpo7 to vpo0 the 8-bit vpo-bus can carry 16 data types in three different formats, selectable by the control registers lcr2 to lcr24 (see also chapter 15, subaddresses 41h to 57h). table 4 vpo-bus data formats and types note 1. the number of valid bytes per line can be less for the sliced data format if standard not recognized (wrong standard or poor input signal). data type number data format data type name number of valid bytes sent per line 0 sliced teletext eurowst, ccst wst625 88 1 sliced european closed caption cc625 8 2 sliced vps vps 56 3 sliced wide screen signalling bits wss 32 4 sliced us teletext (wst) wst525 72 5 sliced us closed caption (line 21) cc525 8 6 yuv4:2:2 video component signal, vbi region test line 1440 7 raw oversampled cvbs data intercast programmable 8 sliced teletext general text 88 9 sliced vitc/ebu time codes (europe) vitc625 26 10 sliced vitc/smpte time codes (usa) vitc625 26 11 reserved reserved -- 12 sliced us nabts nabts 72 13 sliced moji (japanese) japtext 74 14 sliced japanese format switch (l20/22) jfs 56 15 yuv4:2:2 video component signal, active video region active video 1440 for each lcr value from 2 to 23 the data type can be programmed individually. lcr2 to lcr23 refer to line numbers. the selection in lcr24 values is valid for the rest of the corresponding field. the upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). the relationship between lcr values and line numbers can be adjusted via voff8 to voff0 (located in subaddresses 5bh, bit 4 and 5ah, bits 7 to 0). the recommended values are 07h for 50 hz sources and 0ah for 60 hz sources, to accommodate line number conventions as used for pal, secam and ntsc standards; see tables 8 to 11.
1999 jul 01 27 philips semiconductors product speci?cation 9-bit video input processor saa7113h some details about data types: active video (data type 15) component yu v4:2:2 signal, 720 active pixels per line. format and nominal levels are given in fig.23 and table 13. test line (data type 6), is similar to decoded yuv-data as in active video, with two exceptions: C vertical filter (chrominance comb filter for ntsc standards, pal-phase-error correction) within the chrominance processing is disabled C peaking and chrominance trap are bypassed within the luminance processing, if i 2 c-bus bit vblb is set. this data type is defined for future enhancements; it could be activated for lines containing standard test signals within the vertical blanking period; currently the most sources do not contain test lines. this data type is available only in lines with vref = 0, see i 2 c-bus detail section, table 45. format and nominal levels are given in fig.23 and table 13. raw samples (data type 7) oversampled cvbs-signal for intercast applications; the data rate is 27 mhz. the horizontal range is programmable via hsb7 to hsb0, hss7 to hss0 and hdel1 to hdel0; see i 2 c-bus section subaddresses 06h, 07h and 10h and tables 33, 34 and 46. format and nominal levels are given in fig.24 and table 15. sliced data (various standards, data types 0 to 5 and 8 to 14). the format is given in table 17. the data type selections by lcr are overruled by setting vipb (subaddress 11h bit 1) to logic 1. this setting is mainly intended for device production tests. the vpo-bus carries the upper or lower 8 bits of the two adcs depending on the adlsb (subaddress 13h bit 7) setting. the output configuration is done via mode3 to mode0 settings (subaddress 02h bits 3 to 0, see table 27). if the yc-mode is selected, the vpo-bus carries the multiplexed output signals of both adcs, in cvbs-mode the output of only one adc. no timing reference codes are generated in this mode. note : the lsbs (bit 0) of the adcs are available on pins rts0 or rts1. see chapter 15, subaddress 12h for details. the sav/eav timing reference codes define start and end of valid data regions. table 5 sav/eav format bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 1 ?eld bit 1st ?eld: f = 0; 2nd ?eld: f = 1; for vertical timing see tables 6 and 7 vertical blanking bit vbi: v = 1; active video: v = 0; for vertical timing see tables 6 and 7 h = 0 in sav; h = 1 in eav reserved; evaluation not recommended (protection bits according to itu 656) the generation of the h-bit and consequently the timing of sav/eav corresponds to the selected data format. h = 0 during active data region. for all data formats excluding data type 7 (raw data), the length of the active data region is 1440 llc. for the yuv 4:2:2 formats (data types 15 and 6) every clock cycle within this range contains valid data, see table 13. the sliced data stream (various standards, data types 0 to 5 and 8 to 14; see table 17) contains also invalid cycles marked as 00h. the length of the raw data region (data type 7) is programmable via hsb7 to hsb0 and hss7 to hss0 (subaddresses 06h and 07h; see fig.24). during horizontal blanking period between eav and sav the itu-blanking code sequence -80-10-80-10-... is transmitted. the position of the f-bit is constant according to itu 656 (see tables 6 and 7). the v-bit can be generated in four different ways (see tables 6 and 7) controlled via ofts1 and ofts0 (subaddress 10h, bits 7 and 6), vrln (subaddress 10h, bit 3) and lcr2 to lcr24 (subaddresses 41h to 57h). f and v bits change synchronously with the eav code.
1999 jul 01 28 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 6 525 lines/60 hz vertical timing table 7 625 lines/50 hz vertical timing line number f (itu 656) v ofts1 = 0; ofts0 = 0 (itu 656) ofts1 = 0; ofts0 = 1 ofts1 = 1; ofts0 = 0 vrln = 0 vrln = 1 1 to 3 1 1 1 1 according to selected data type via lcr2 to lcr24 (subaddresses 41h to 57h): data types 0 to 14: v = 1; data type 15: v = 0 4to190111 200011 210010 22 to 261 0 0 0 0 262 0 0 1 0 263 0 0 1 1 264 and 265 0 1 1 1 266 to 282 1 1 1 1 283 1 0 1 1 284 1 0 1 0 285 to 524 1 0 0 0 525 1 0 1 0 line number f (itu 656) v ofts1 = 0; ofts0 = 0 (itu 656) ofts1 = 0; ofts0 = 1 ofts1 = 1; ofts0 = 0 vrln = 0 vrln = 1 1 to 22 0 1 1 1 according to selected data type via lcr2 to lcr24 (subaddresses 41h to 57h): data types 0 to 14: v = 1; data type 15: v = 0 230010 24 to 309 0 0 0 0 310 0 0 1 0 311 and 312 0 1 1 1 313 to 335 1 1 1 1 336 1 0 1 0 337 to 622 1 0 0 0 623 1 0 1 0 624 and 625 1 1 1 1
1999 jul 01 29 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 8 relationship of lcr to line numbers in 525 lines/60 hz systems (part 1) table 9 relationship of lcr to line numbers in 525 lines/60 hz systems (part 2) table 10 relationship of lcr to line numbers in 625 lines/50 hz systems (part 1) vertical line offset voff8 to voff0 = 00ah; horizontal pixel offset hoff10 to hoff0 = 354h, foff = 1, fiset = 1 line number (1st ?eld) 519520521522523524525123456789 active video equalization pulses serration pulses equalization pulses line number (2nd ?eld) 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 active video equalization pulses serration pulses equalization pulses lcr (voff = 00ah; hoff = 354h; foff = 1; fiset = 1) 24 23456789 vertical line offset voff8 to voff0 = 00ah; horizontal pixel offset hoff10 to hoff0 = 354h, foff = 1, fiset = 1 line number (1st ?eld) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 nominal vbi-lines f1 active video line number (2nd ?eld) 273 274 275 276 277 278 279 280 281 282 283 284 285 286 nominal vbi-lines f2 active video lcr (voff = 00ah; hoff = 354h; foff = 1; fiset = 1) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 vertical line offset voff8 to voff0 = 007h; horizontal pixel offset hoff10 to hoff0 = 354h, foff = 1, fiset = 0 line number (1st ?eld) 621 622 623 624 625 12345 active video equalization pulses serration pulses equalization pulses line number (2nd ?eld) 309 310 311 312 313 314 315 316 317 318 active video equalization pulses serration pulses equalization pulses lcr (voff = 007h; hoff = 354h; foff = 1; fiset = 0) 24 2345
1999 jul 01 30 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 11 relationship of lcr to line numbers in 625 lines/50 hz systems (part 2) table 12 location of related programming registers vertical line offset voff8 to voff0 = 007h; horizontal pixel offset hoff10 to hoff0 = 354h, foff = 1, fiset = 0 line number (1st ?eld) 6 7 8 9 10111213141516171819202122232425 nominal vbi-lines f1 active video line number (2nd ?eld) 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 nominal vbi-lines f2 active video lcr (voff = 007h; hoff = 354h; foff = 1; fiset = 0) 6 7 8 9 101112131415161718192021222324 name subaddress, bits voff8 to voff0 5b, d4 and 5a, d7 to d0 hoff10 to hoff0 5b, d2 to d0 and 59, d7 to d0 foff 5b, d7 fiset 40, d7
1999 jul 01 31 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 13 yuv data format on the 8-bit vpo-bus (data types 6 and 15) table 14 explanation to table 13 blanking period timing reference code 720 pixels yu v4:2:2 data timing reference code blanking period ... 80 10 ff 00 00 sav c b 0y0c r 0y1c b 2 y2 ... c r 718 y719 ff 00 00 eav 80 10 ... name explanation sav start of active video range; see tables 5 to 7 c b n u (b - y) colour difference component, pixel number n = 0, 2, 4 to 718 yn y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 c r n v (r - y) colour difference component, pixel number n = 0, 2, 4 to 718 eav end of active video range; see tables 5 to 7 fig.23 yuv 4 : 2 : 2 levels on the 8-bit vpo-bus (data types 6 and 15). equations for modification to the yuv levels via bcs control i 2 c-bus bytes brig, cont and satn. luminance: chrominance: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu-601/656 standard. y out int cont 71 ----------------- - y128 C () brig + = uv out int satn 64 ---------------- - c r c b , 128 C () 128 + = handbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 white black u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mgc634 a. y output range. b. u output range (c b ). c. v output range (c r ).
1999 jul 01 32 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 15 raw data format on the 8-bit vpo-bus (data type 8) table 16 explanation to table 15 blanking period timing reference code oversampled cvbs samples timing reference code blanking period ... 80 10 ff 00 00 sav y0 y1 y2 y3 y4 y5 ... yn - 1 yn ff 00 00 eav 80 10 ... name explanation sav start of raw sample range; see tables 5 to 7 yi oversampled raw sample stream (cvbs signal), n = 0, 1, 2, 3 to n; n is programmable via hsb and hss; see sections 15.2.7 and 15.2.8 eav end of raw sample range; see tables 5 to 7 fig.24 raw data levels on the 8-bit vpo-bus (data type 8). vbi data levels are not dependent on bcs settings. handbook, full pagewidth luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync mgd700 a. for sources containing 7.5 ire black level offset (e.g. ntsc - m). b. for sources not containing black level offset.
1999 jul 01 33 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 17 sliced data format on the 8-bit vpo-bus (data types 0 to 5 and 8 to 14) table 18 explanation to table 17 notes 1. inverted ep (bit 7); for ep see note 2. 2. even parity (bit 6) of bits 5 to 0. 3. odd parity (bit 7) of bits 6 to 0. blanking period timing reference code internal header sliced data timing reference code blanking period ... 80 10 ff 00 00 sav sdid dc idi1 idi2 dln1 dhn1 ... dlnn dhnn ff 00 00 eav 80 10 ... name explanation sav start of active data; see tables 5 to 7 sdid sliced data identi?cation: nep (1) , ep (2) , sdid5 to sdid0, freely programmable via i 2 c-bus subaddress 5eh, d5 to d0, e. g. to be used as source identi?er dc dword count: nep (1) , ep (2) , dc5 to dc0; dc is inserted for software compatibility reasons to saa7112, but does not represent any relevant information for saa7113h applications. dc describes the number of succeeding 32-bit words: dc = 1 4 (c + n), where c = 2 (the two data identi?cation bytes idi1 and idi2) and n = number of decoded bytes according to the chosen text standard. as the sliced data are transmitted nibble wise, the maximum number of bytes transmitted (nbt) starting at idi1 result s to: nbs = (dc 8) - 2 dc can vary between 1 and 11, depending on the selected data type. note that the number of bytes actually transmitted can be less than nbt for two reasons: 1. result of dc would result to a non-integer value (dc is always rounded up) 2. standard not recognized (wrong standard or poor input signal) idi1 internal data identi?cation 1: op (3) , fid (?el d 1 = 0, ?eld 2 = 1), linenumber8 to linenumber3 idi2 internal data identi?cation 2: op (3) , linenumber2 to linenumber0, datatype3 to datatype0; see table 4 dlnn sliced data low nibble, format: nep (1) , ep (2) , d3 to d0, 1, 1 dlhn sliced data high nibble, format: nep (1) , ep (2) , d7 to d4, 1, 1 eav end of active data; see tables 5 to 7
1999 jul 01 34 philips semiconductors product speci?cation 9-bit video input processor saa7113h 8.11 rtco output the real-time control and status output signal contains serial information about the actual system clock (increment of the hpll), subcarrier frequency, increment and phase (via reset) of the fsc-pll and pal sequence bit. the signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding. the saa7113h supports rtc level 3.1 (see external document rtc functional description , available on request). 8.12 rts0, rts1 terminals these two pins are multi functional inputs/output controlled by i 2 c-bus bits rtse03 to rtse00 and rtse13 to rtse10, located in subaddress 12h; see tables 49 and 50. the rts0 terminal can be strapped to ground via a 3.3 k w resistor to change the i 2 c-bus slave address from default 4ah/4bh to 48h/49h (the strapping information is read only during the reset sequence). the rts1 terminal can be configured as data output to 3-state (dot) input by rtse13 to rtse10 = 0000 to control the vpo port (bits 7 to 0) via hardware according to table 19. table 19 digital output control via rts1 (enabled by bits rtse13 to rtse10 = 0) 9 boundary scan test the saa7113h has built in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the saa7113h follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the bst functions bypass, extest, intest, sample, clamp and idcode are all supported (see table 20). details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the saa7113h is available on request. oeyc dot (rts1) vpo7 to vpo0 00 z 1 0 active 01 z 11 z table 20 bst instructions supported by the saa7113h instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no support for customers available). user1 this private instruction allows testing by the manufacturer (no support for customers available).
1999 jul 01 35 philips semiconductors product speci?cation 9-bit video input processor saa7113h 9.1 initialization of boundary scan circuit the tap (test access port) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst pin low. 9.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.25. fig.25 32 bits of identification code. handbook, full pagewidth mhb332 00000010101 0111000100010011 nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1
1999 jul 01 36 philips semiconductors product speci?cation 9-bit video input processor saa7113h 10 limiting values in accordance with the absolute maximum rating system (iec 134); all ground pins connected together and all supply pins connected together. note 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 11 thermal characteristics symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v ia input voltage at analog inputs - 0.5 v dda + 0.5 (4.6 max) v v oa output voltage at analog output - 0.5 v dda + 0.5 v v id input voltage at digital inputs and outputs outputs in 3-state - 0.5 +5.5 v v od output voltage at digital outputs outputs active - 0.5 v ddd + 0.5 v d v ss voltage difference between v ssa(all) and v ss(all) - 100 mv t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c t amb(bias) operating ambient temperature under bias - 10 +80 c v esd electrostatic discharge all pins note 1 - 2000 +2000 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 64 k/w
1999 jul 01 37 philips semiconductors product speci?cation 9-bit video input processor saa7113h 12 characteristics v ddd = 3.0 to 3.6 v; v dda = 3.1 to 3.5 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 32 35 ma p d digital power - 0.10 - w v dda analog supply voltage v dda v ddd + 200 mv 3.1 3.3 3.5 v i dda analog supply current aosl1 to aosl0 = 0 - 90 - ma p a analog power - 0.30 - w p a+d analog and digital power - 0.40 - w p a+d(pd) analog and digital power in power-down mode ce connected to ground - 0.07 - w analog part i clamp clamping current v i = 0.9 v dc - 8 -m a v i(p-p) input voltage (peak-to-peak value) for normal video levels 1 v (p-p), termination 18/56 w and ac coupling required; coupling capacitor = 47 nf 0.5 0.7 1.4 v ? z i ? input impedance clamping current off 200 -- k w c i input capacitance -- 10 pf a cs channel crosstalk f i = 5 mhz --- 50 db 9-bit analog-to-digital converters b bandwidth at - 3db - 7 - mhz f diff differential phase (ampli?er plus anti-alias ?lter bypassed) - 2 - deg g diff differential gain (ampli?er plus anti-alias ?lter bypassed) - 2 - % f clk(adc) adc clock frequency 12.8 - 14.3 mhz dle dc differential linearity error - 0.7 - lsb ile dc integral linearity error - 1 - lsb
1999 jul 01 38 philips semiconductors product speci?cation 9-bit video input processor saa7113h digital inputs v il(scl,sda) low-level input voltage pins sda and scl - 0.5 - +0.3v ddd v v ih(scl,sda) high-level input voltage pins sda and scl 0.7v ddd - v ddd + 0.5 v v il(xtal) low-level cmos input voltage pin xtali - 0.3 - +0.8 v v ih(xtal) high-level cmos input voltage pin xtali 2.0 - v ddd + 0.3 v v il(n) low-level input voltage all other inputs - 0.3 - +0.8 v v ih(n) high-level input voltage all other inputs 2.0 - 5.5 v i li input leakage current -- 10 m a c i input capacitance outputs at 3-state -- 8pf c i(n) input capacitance all other inputs -- 5pf digital outputs v ol(scl,sda) low-level output voltage pins sda and scl sda/scl at 3 ma (6 ma) sink current -- 0.4 (0.6) v v ol low-level output voltage v ddd = max; i ol =2ma 0 - 0.4 v v oh high-level output voltage v ddd = min; i oh = - 2 ma 2.4 - v ddd + 0.5 v v ol(clk) low-level output voltage for llc clock - 0.5 - +0.6 v v oh(clk) high-level output voltage for llc clock 2.4 - v ddd + 0.5 v rts1 (dot) input timing t su;dat input data set-up time 13 -- ns t hd;dat input data hold time 3 -- ns data and control output timing; note 1 c l output load capacitance 15 - 40 pf t ohd;dat output hold time c l =15pf 4 -- ns t pd propagation delay c l =25pf -- 22 ns t pdz propagation delay to 3-state -- 22 ns symbol parameter conditions min. typ. max. unit
1999 jul 01 39 philips semiconductors product speci?cation 9-bit video input processor saa7113h notes 1. the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l = 50 pf. 2. the effects of rise and fall times are included in the calculation of t ohd;dat , t pd and t pdz . timings and levels refer to drawings and conditions illustrated in fig.26. 3. order number: philips 4322 143 05291. clock output timing (llc); note 2 c l(llc) output load capacitance 15 - 40 pf t cy cycle time llc 35 - 39 ns d llc duty factors for t llch /t llc c l =25pf 40 - 60 % t r rise time llc -- 5ns t f fall time llc -- 5ns clock input timing (xtali) d xtali duty factor for t xtalih /t xtali nominal frequency 40 - 60 % horizontal pll f hn nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f h /f hn permissible static deviation -- 5.7 % subcarrier pll f scn nominal subcarrier frequency pal bghin - 4433619 - hz ntsc m; ntsc-japan - 3579545 - hz pal m - 3575612 - hz combination-pal n - 3582056 - hz d f sc lock-in range 400 -- hz crystal oscillator f n nominal frequency 3rd harmonic; note 3 - 24.576 - mhz d f/f n permissible nominal frequency deviation -- 50 10 - 6 d tf/f n(t) permissible nominal frequency deviation with temperature -- 20 10 - 6 c rystal specification (x1) t amb(x1) operating ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff c 0 parallel capacitance - 3.5 20% - pf symbol parameter conditions min. typ. max. unit
1999 jul 01 40 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 21 processing delay function typical analog delay ai22 -> adcin (aout) (ns) digital delay adcin -> vpo (llc clocks); ydel2 to ydel0 = 0 without ampli?er or anti-alias ?lter 15 157 with ampli?er, without anti-alias ?lter 25 with ampli?er and anti-alias ?lter 75
1999 jul 01 41 philips semiconductors product speci?cation 9-bit video input processor saa7113h 13 timing diagrams fig.26 clock/data output timing. handbook, full pagewidth 2.4 v t llc t f t pd t ohd;dat t llcl t llch outputs vpo, rtco, rts0, rts1 clock output llc t r 0.6 v 2.6 v 1.5 v 0.6 v mhb333 fig.27 rts1 input (dot) timing. handbook, full pagewidth mhb334 t pd t pdz t ohd t hd t su llc rts1 (dot) vpo
1999 jul 01 42 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.28 horizontal timing diagram. (1) plin is switched to outputs rts0 and/or rts1 via i 2 c-bus bits rtse13 to rtse10 and/or rtse03 to rtse00. (2) see table 21. handbook, full pagewidth 0 108 - 107 107 - 106 mhb335 cvbs input raw data on vpo-bus 28 1/llc 157 1/llc 15 2/llc y-data on vpo-bus rts0/1 href (50 hz) 12 2/llc 720 2/llc 144 2/llc 11 2/llc 138 2/llc 720 2/llc burst burst rts0/1 (plin) (1) processing delay cvbs->vpo (2) 0 0 4/llc rts0/1 href (60 hz) rts0/1 hs (60 hz) sync clipped 16 2/llc rts0/1 hs (50 hz) programming range (step size: 8/llc) rts0/1 hs (60 hz) programming range (step size: 8/llc) rts0/1 hs 55 2/llc
1999 jul 01 43 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.29 vertical timing diagram for 50 hz [nominal input signal, vnl in normal mode (vnoi = 00), hpll in vcr or fast mode (htc = 01 or 11)]. href: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = 7h. odd: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = ah. vs: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = bh. v123: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = ch. vref: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = eh. fid: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = fh. (1) vref range short or long can be programmed via i 2 c-bus bit vrln. the luminance peaking and the chrominance trap are bypassed during vref = 0 if i 2 c-bus bit vblb is set to logic 1. the chrominance delay line (chrominance-comb filter for ntsc, phase error correcting for pal) is disabled during vref = 0. (2) fid changing line number and polarity programmable via vsta8 to vsta0 and fidp, see table 52. (3) the inactive going edge of the v123-signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd . if href is inactive during the falling edge of v123, the field is even . the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. handbook, full pagewidth 313 314 315 316 317 318 319 335 336 1234567822 625 rts0/1 href input cvbs (b) 2nd field (a) 1st field vrln = 1 (1) vrln = 0 (1) rts0/1 vref rts0/1 vref vrln = 0 (1) 624 623 622 23 rts0/1 href input cvbs 312 311 310 337 mhb336 499 2/llc rts0/1 vs rts0/1 odd rts0/1 v123 (3) rts0/1 odd rts0/1 fid (2) 320 rts0/1 vs rts0/1 v123 (3) rts0/1 fid (2) 67 2/llc vrln = 1 (1) rts0/1 vref rts0/1 vref
1999 jul 01 44 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.30 vertical timing diagram for 60 hz [nominal input signal, vnl in normal mode (vnoi = 00), hpll in vcr or fast mode (htc = 01 or 11)]. href: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = 7h. odd: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = ah. vs: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to 00 and/or rtse13 to rtse10 = bh. v123: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = ch. vref: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = eh. fid: selectable on rts0 and/or rts1 via i 2 c-bus bits rtse03 to rtse00 and/or rtse13 to rtse10 = fh. (1) line numbers in parenthesis refer to itu line counting. (2) vref range short or long can be programmed via i 2 c-bus bit vrln. the luminance peaking and the chrominance trap are bypassed during vref = 0 if i 2 c-bus bit vblb is set to logic 1. the chrominance delay line (chrominance-comb filter for ntsc, phase error correcting for pal) is disabled during vref = 0. (3) fid changing line number and polarity programmable via vsta8 to vsta0 and fidp, see table 52. (4) the inactive going edge of the v123-signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd . if href is inactive during the falling edge of v123, the field is even . the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. handbook, full pagewidth rts0/1 vs vrln = 1 (2) (b) 2nd field (a) 1st field input cvbs (4) (5) (6) (7) (8) (9) (10) (11) (20) (3) (2) (1) (525) (21) (22) (1) vrln = 1 (3) (2) vrln = 0 (3) (2) 1234567 8 17 525 524 523 522 18 19 (266) (267) (268) (269) (270) (271) (272) (273) (274) (283) (284) (265) (264) (263) (262) 263 264 265 266 267 268 269 270 271 280 281 262 261 260 259 (285) (1) 282 mhb337 520 2/llc rts0/1 odd 81 2/llc vrln = 0 (2) rst0/1 href rts0/1 vref rts0/1 vref rts0/1 vref rts0/1 vref rts0/1 vs rts0/1 href input cvbs rts0/1 odd rts0/1 v123 (4) rts0/1 fid (3) rts0/1 v123 (4) rts0/1 fid (3)
1999 jul 01 45 philips semiconductors product speci?cation 9-bit video input processor saa7113h 14 application information fig.31 application diagram. handbook, full pagewidth q1 (24.576 mhz) scl ce v ddd ai22 sda vpo3 vpo4 vpo5 rtco vpo0 vpo1 vpo2 llc aout rts0 rts1 vpo7 v ssd v ssd v dda v ddd v ssd vpo6 v ssd saa7113h r4 c4 c7 100 nf 100 nf 100 nf c8 c9 c12 c13 c14 c15 v dda0 v dda1 v dda2 v ddde1 v ddde2 v dddi v ddda tms tdi tdo tck c17 l1 10 m h c16 1 nf 10 pf 10 pf c18 r5 1 k w 33 29 34 18 38 42 3 10 12 14 15 19 25 22 20 21 27 26 9 17 13 8 37 35 30 28 16 6 41 2 11 36 39 1 24 23 5 40 32 31 xtal xtali mhb349 bst n.c. n.c. n.c. 100 nf 100 nf 100 nf 100 nf r3 c3 ai21 r2 c2 43 ai12 r1 56 w c1 47 nf v ssa v ssa 7 44 ai11 4 trst r10 r9 r8 r7 18 w 56 w 47 nf v ssa 18 w c19 ai1d 47 nf v ssa c20 ai2d 47 nf 56 w 47 nf v ssa 18 w 56 w 47 nf v ssa v ssa 18 w v ssa0 v ssa1 agnd v ssde1 v ssde2 v ssa2 v ssda v ssdi
1999 jul 01 46 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15 i 2 c-bus description 15.1 i 2 c-bus format fig.32 oscillator application. order number: philips 4322 143 05291. handbook, full pagewidth xtal xtali 31 32 mhb338 xtal l = 10 m h 20% c = 10 pf c = 10 pf c = 1 nf quartz (3rd harmonic) 24.576 mhz xtali 31 32 saa7113h saa7113h a. with quartz crystal. b. with external clock. fig.33 write procedure. handbook, full pagewidth ack-s ack-s data slave address w data transferred (n bytes + acknowledge) mhb339 p s ack-s subaddress
1999 jul 01 47 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 22 description of i 2 c-bus format; note 1 notes 1. the saa7113h supports the fast mode i 2 c-bus specification extension (data rate up to 400 kbits/s). 2. if more than one byte data is transmitted the subaddress pointer is automatically incremented. code description s start condition sr repeated start condition slave address w 0100 1010 (= 4ah, default) or 0100 1000 (= 48h, if pin rts0 strapped to ground via a 3.3 k w resistor) slave address r 0100 1011 (= 4bh, default) or 0100 1001 (= 49h, if pin rts0 strapped to ground via a 3.3 k w resistor) ack-s acknowledge generated by the slave ack-m acknowledge generated by the master subaddress subaddress byte; see table 24 data data byte; see table 24; note 2 p stop condition x = lsb slave address read/write control bit; x = 0, order to write (the circuit is slave receiver); x = 1, order to read (the circuit is slave transmitter) subaddresses 00h chip version read only 01h to 05h front-end part read and write 06h to 13h decoder part read and write 14h reserved - 15h to 17h decoder part read and write 18h to 1eh reserved - 1fh video decoder status byte read only 20h to 3fh reserved - 40h to 60h general purpose data slicer read and write 60h to 62h general purpose data slicer status read only 63h to ffh reserved - fig.34 read procedure (combined format). handbook, full pagewidth ack-s ack-m slave address r mhb340 p sr ack-s ack-s data subaddress slave address w s data transferred (n bytes + acknowledge)
1999 jul 01 48 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 23 slave address read write description 4bh 4ah default 49h 48h rts0 strapped to ground
1999 jul 01 49 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 24 i 2 c-bus receiver/transmitter overview register function sub- addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 chip version (read only) 00 id07 id06 id05 id04 ---- increment delay 01 (1) (1) (1) (1) idel3 idel2 idel1 idel0 analog input control 1 02 fuse1 fuse0 gudl1 gudl0 mode3 mode2 mode1 mode0 analog input control 2 03 (1) hlnrs vbsl wpoff holdg gafix gai28 gai18 analog input control 3 04 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 analog input control 4 05 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 horizontal sync start 06 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 horizontal sync stop 07 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 sync control 08 aufd fsel foet htc1 htc0 hpll vnoi1 vnoi0 luminance control 09 byps pref bpss1 bpss0 vblb uptcv aper1 aper0 luminance brightness 0a brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast 0b cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation 0c satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 chroma hue control 0d huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 chroma control 0e cdto cstd2 cstd1 cstd0 dccf fctc chbw1 chbw0 chroma gain control 0f acgc cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 format/delay control 10 ofts1 ofts0 hdel1 hdel0 vrln ydel2 ydel1 ydel0 output control 1 11 gpsw1 cm99 gpsw0 hlsel oeyc oert vipb colo output control 2 12 rtse13 rtse12 rtse11 rtse10 rtse03 rtse02 rtse01 rtse00 output control 3 13 adlsb (1) (1) oldsb fidp (1) aosl1 aosl0 reserved 14 (1) (1) (1) (1) (1) (1) (1) (1) v_gate1_start 15 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 v_gate1_stop 16 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 v_gate1_msb 17 (1) (1) (1) (1) (1) (1) vsto8 vsta8 reserved 18 to 1e (1) (1) (1) (1) (1) (1) (1) (1) status byte (read only, oldsb = 0) 1f intl hlvln fidt glimt glimb wipa copro rdcap status byte (read only, oldsb = 1) 1f intl hlck fidt glimt glimb wipa sltca code reserved 20 to 3f (1) (1) (1) (1) (1) (1) (1) (1)
1999 jul 01 50 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... note 1. all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. ac1 40 fiset ham_n fce hunt_n (1) clksel1 clksel0 (1) lcr2 41 lcr02_7 lcr02_6 lcr02_5 lcr02_4 lcr02_3 lcr02_2 lcr02_1 lcr02_0 lcr3 to lcr23 42 to 56 lcrn_7 lcrn_6 lcrn_5 lcrn_4 lcrn_3 lcrn_2 lcrn_1 lcrn_0 lcr24 57 lcr24_7 lcr24_6 lcr24_5 lcr24_4 lcr24_3 lcr24_2 lcr24_1 lcr24_0 fc 58 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 hoff 59 hoff7 hoff6 hoff5 hoff4 hoff3 hoff2 hoff1 hoff0 voff 5a voff7 voff6 voff5 voff4 voff3 voff2 voff1 voff0 hvoff 5b foff (1) (1) voff8 (1) hoff10 hoff9 hoff8 for testability 5c (1) (1) (1) (1) (1) (1) (1) (1) reserved 5d (1) (1) (1) (1) (1) (1) (1) (1) sliced data identi?cation code sdid 5e (1) (1) sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 reserved 5f (1) (1) (1) (1) (1) (1) (1) (1) dr (read only) 60 - fc8v fc7v vpsv ppv ccv -- ln1 (read only) 61 -- f21_n ln8 ln7 ln6 ln5 ln4 ln2 (read only) 62 ln3 ln2 ln1 ln0 dt3 dt2 dt1 dt0 reserved for future extensions 63 to ff (1) (1) (1) (1) (1) (1) (1) (1) register function sub- addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
1999 jul 01 51 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2 i 2 c-bus detail the i 2 c-bus receiver slave address is 48h/49h. subaddresses 14h, 18h to 1eh, 20h to 3fh and 63h to ffh are reserved. 15.2.1 s ubaddress 00h ( read only register ) table 25 chip version sa 00 function logic levels id07 id06 id05 id04 chip version (cv) cv3 cv2 cv1 cv0 15.2.2 s ubaddress 01h table 26 horizontal increment delay the programming of the horizontal increment delay is used to match internal processing delays to the delay of the adc. use recommended position only. function idel3 idel2 idel1 idel0 no update 1111 minimum delay 1110 recommended position 1000 maximum delay 0000 15.2.3 s ubaddress 02h table 27 analog control 1 sa 02 notes 1. mode select (see figs 35 to 42). 2. to take full advantage of the yc-modes 6 to 9 the i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). function (1) control bits d3 to d0 mode 3 mode 2 mode 1 mode 0 mode 0: cvbs (automatic gain) from ai11 (pin 4) 0000 mode 1: cvbs (automatic gain) from ai12 (pin 7) 0001 mode 2: cvbs (automatic gain) from ai21 (pin 43) 0010 mode 3: cvbs (automatic gain) from ai22 (pin 1) 0011 mode 4: reserved 0100 mode 5: reserved 0101 mode 6: y (automatic gain) from ai11 (pin 4) + c (gain adjustable via gai28 to gai20) from ai21 (pin 43); note 2 0110 mode 7: y (automatic gain) from ai12 (pin 7) + c (gain adjustable via gai28 to gai20) from ai22 (pin 1); note 2 0111 mode 8: y (automatic gain) from ai11 (pin 4) + c (gain adapted to y gain) from ai21 (pin 43); note 2 1000 mode 9: y (automatic gain) from ai12 (pin 7) + c (gain adapted to y gain) from ai22 (pin 1); note 2 1001 modes 10 to 15: reserved 1111
1999 jul 01 52 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 28 analog control 1 sa 02, d5 and d4 (see fig.7) table 29 analog control 1 sa 02, d7 and d6 (see fig.6) update hysteresis for 9-bit gain control bits d5 and d4 gudl 1 gudl 0 off 0 0 1 lsb 0 1 2 lsb 1 0 3 lsb 1 1 analog function select fuse control bits d7 and d6 fuse 1 fuse 0 ampli?er plus anti-alias ?lter bypassed 0 0 01 ampli?er active 1 0 ampli?er plus anti-alias ?lter active 1 1
1999 jul 01 53 philips semiconductors product speci?cation 9-bit video input processor saa7113h fig.35 mode 0; cvbs (automatic gain). handbook, halfpage mhb341 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.36 mode 1; cvbs (automatic gain). handbook, halfpage mhb342 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.37 mode 2; cvbs (automatic gain). handbook, halfpage mhb343 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.38 mode 3; cvbs (automatic gain). handbook, halfpage mhb344 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.39 mode 6; y + c (gain channel 2 adjusted via gai2). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb345 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.40 mode 7; y + c (gain channel 2 adjusted via gai2). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb346 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.41 mode 8; y + c (gain channel 2 adapted to y gain). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb347 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma fig.42 mode 9; y + c (gain channel 2 adapted to y gain). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). mhb348 handbook, halfpage ai22 ai21 ai12 ai11 ad2 ad1 chroma luma
1999 jul 01 54 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.4 s ubaddress 03h table 30 analog control 2 (aico2) sa 03 15.2.5 s ubaddress 04h table 31 gain control analog (aico3); static gain control channel 1 gai1 sa 04, d7 to d0 function logic level data bit static gain control channel 1 (gai18) (see sa 04) sign bit of gain control see table 31 d0 static gain control channel 2 (gai28) (see sa 05) sign bit of gain control see table 32 d1 gain control ?x (gafix) automatic gain controlled by mode3 to mode0 0 d2 gain is user programmable via gai1 + gai2 1 d2 automatic gain control integration (holdg) agc active 0d3 agc integration hold (freeze) 1 d3 white peak off (wpoff) white peak control active 0 d4 white peak off 1 d4 agc hold during vertical blanking period (vbsl) short vertical blanking (agc disabled during equalization and serration pulses) 0d5 long vertical blanking (agc disabled from start of pre-equalization pulses until start of active video (line 22 for 60 hz, line 24 for 50 hz) 1d5 hl not reference select (hlnrs) normal clamping if decoder is in unlocked state 0 d6 reference select if decoder is in unlocked state 1 d6 decimal value gain (db) sign bit control bits d7 to d0 gai18 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 0... ?- 3000000000 ...117... ? 0001110101 ...511 ? 6111111111
1999 jul 01 55 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.6 s ubaddress 05h table 32 gain control analog (aico4); static gain control channel 2 gai2 sa 05, d7 to d0 15.2.7 s ubaddress 06h table 33 horizontal sync begin sa 06, d7 to d0 15.2.8 s ubaddress 07h table 34 horizontal sync stop sa 07, d7 to d0 decimal value gain (db) sign bit (sa 03, d1) control bits d7 to d0 gai28 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 0... ?- 3 0 00000000 ...117... ? 0 0 01110101 ...511 ? 6 1 11111111 delay time (step size = 8/llc) control bits d7 to d0 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz) recommended value for raw data type; see fig.24 1 1 101001 delay time (step size = 8/llc) control bits d7 to d0 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz) recommended value for raw data type; see fig.24 0 0 001101
1999 jul 01 56 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.9 s ubaddress 08h table 35 sync control sa 08, d7 to d5, d3 to d0 function control bit logic level data bit vertical noise reduction (vnoi) normal mode ( recommended setting ) vnoi1 0 d1 vnoi0 0 d0 fast mode [applicable for stable sources only; automatic ?eld detection (aufd) must be disabled] vnoi1 0 d1 vnoi0 1 d0 free running mode vnoi1 1 d1 vnoi0 0 d0 vertical noise reduction bypassed vnoi1 1 d1 vnoi0 1 d0 horizontal pll (hpll) pll closed hpll 0 d2 pll open; horizontal frequency ?xed hpll 1 d2 horizontal time constant selection (htc1 and htc0) tv mode (recommended for poor quality tv signals only; do not use for new applications) htc1 and htc0 00 d4 and d3 vtr mode (recommended if a de?ection control circuit is directly connected to saa7113h) htc1 and htc0 01 d4 and d3 reserved htc1 and htc0 10 d4 and d3 fast locking mode ( recommended setting ) htc1 and htc0 11 d4 and d3 forced odd/even toggle foet odd/even signal toggles only with interlaced source foet 0 d5 odd/even signal toggles ?eldwise even if source is non-interlaced foet 1 d5 field selection (fsel) 50 hz, 625 lines fsel 0 d6 60 hz, 525 lines fsel 1 d6 automatic ?eld detection (aufd) field state directly controlled via fsel aufd 0 d7 automatic ?eld detection aufd 1 d7
1999 jul 01 57 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.10 s ubaddress 09h table 36 luminance control sa 09, d7 to d0 note 1. not to be used with bypassed chrominance trap. function aper/bpss bit logic level data bit aperture factor (aper); see figs 12 to 17 aperture factor = 0 aper1 0 d1 aper0 0 d0 aperture factor = 0.25 aper1 0 d1 aper0 1 d0 aperture factor = 0.5 aper1 1 d1 aper0 0 d0 aperture factor = 1.0 aper1 1 d1 aper0 1 d0 update time interval for analog agc value (uptcv) horizontal update (once per line) uptcv 0 d2 vertical update (once per ?eld) uptcv 1 d2 vertical blanking luminance bypass (vblb) active luminance processing vblb 0 d3 chrominance trap and peaking stage are disabled during vbi lines determined by vref = 0; see table 45 vblb 1 d3 aperture band-pass (centre frequency) (bpss) centre frequency = 4.1 mhz bpss1 0 d5 bpss0 0 d4 centre frequency = 3.8 mhz; note 1 bpss1 0 d5 bpss0 1 d4 centre frequency = 2.6 mhz; note 1 bpss1 1 d5 bpss0 0 d4 centre frequency = 2.9 mhz; note 1 bpss1 1 d5 bpss0 1 d4 pre?lter active (pref); see figs 12 to 17 bypassed pref 0 d6 active pref 1 d6 chrominance trap bypass (byps) chrominance trap active; default for cvbs mode byps 0 d7 chrominance trap bypassed; default for s-video mode byps 1 d7
1999 jul 01 58 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.11 s ubaddress 0ah table 37 luminance brightness control brig7 to brig0 sa 0a 15.2.12 s ubaddress 0bh table 38 luminance contrast control cont7 to cont0 sa 0b 15.2.13 s ubaddress 0ch table 39 chrominance saturation control satn7 to satn0 sa 0c 15.2.14 s ubaddress 0dh table 40 chrominance hue control huec7 to huec0 sa 0d offset control bits d7 to d0 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 255 (bright) 11111111 128 (ccir level) 10000000 0 (dark) 00000000 gain control bits d7 to d0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 1.999 (maximum) 01111111 1.109 (ccir level) 01000111 1.0 01000000 0 (luminance off) 00000000 - 1 (inverse luminance) 11000000 - 2 (inverse luminance) 10000000 gain control bits d7 to d0 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 1.999 (maximum) 01111111 1.0 (ccir level) 01000000 0 (colour off) 00000000 - 1 (inverse chrominance) 11000000 - 2 (inverse chrominance) 10000000 hue phase (deg) control bits d7 to d0 huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6... 01111111 ...0... 00000000 ... - 180 10000000
1999 jul 01 59 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.15 s ubaddress 0eh table 41 chrominance control sa 0e function chbw/cstd bit logic level data bit 50 hz 60 hz chrominance bandwidth (chbw0 and chbw1) small bandwidth ( ? 620 khz) chbw1 0 d1 chbw0 0 d0 nominal bandwidth ( ? 800 khz) chbw1 0 d1 chbw0 1 d0 medium bandwidth ( ? 920 khz) chbw1 1 d1 chbw0 0 d0 wide bandwidth ( ? 1000 khz) chbw1 1 d1 chbw0 1 d0 fast colour time constant (fctc) nominal time constant fctc 0 d2 fast time constant fctc 1 d2 disable chrominance comb ?lter (dccf) chrominance comb ?lter on (during lines determined by vref = 1; see table 45) dccf 0 d3 chrominance comb ?lter permanently off dccf 1 d3 colour standard selection (cstd0 to cstd2); logic levels 100, 110 and 111 are reserved, do not use pal bghin ntsc m (or ntsc-japan with special level adjustment: brightness subaddress 0ah = 95h; contrast subaddress 0bh = 48h) cstd2 0 d6 cstd1 0 d5 cstd0 0 d4 ntsc 4.43 (50 hz) pal 4.43 (60 hz) cstd2 0 d6 cstd1 0 d5 cstd0 1 d4 combination-pal n ntsc 4.43 (60 hz) cstd2 0 d6 cstd1 1 d5 cstd0 0 d4 ntsc n pal m cstd2 0 d6 cstd1 1 d5 cstd0 1 d4 secam reserved cstd2 1 d6 cstd1 0 d5 cstd0 1 d4
1999 jul 01 60 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.16 s ubaddress 0fh table 42 chrominance gain control sa 0f (d6 to d0) table 43 chrominance gain control sa 0f (d7) 15.2.17 s ubaddress 10h table 44 format/delay control sa 10 (d2 to d0) clear dto (cdto) disabled cdto 0 d7 every time cdto is set, the internal subcarrier dto phase is reset to 0 and the rtco output generates a logic 0 at time slot 68 (see external document rtc functional description , available on request). so an identical subcarrier phase can be generated by an external device (e.g. an encoder). cdto 1 d7 chrominance gain value (if acgc is set to logic 1) control bits d6 to d0 cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 minimum gain (0.5) 0 000000 nominal gain (1.125) 0 100100 maximum gain (7.5) 1 111111 automatic chrominance gain control acgc d7 acgc on 0 programmable gain via cgain6 to cgain0 1 luminance delay compensation (steps in 2/llc) control bits d2 to d0 ydel2 ydel1 ydel0 - 4... 1 0 0 ...0... 0 0 0 ...3 0 1 1 function chbw/cstd bit logic level data bit 50 hz 60 hz
1999 jul 01 61 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 45 vref pulse position and length vrln sa 10 (d3) note 1. the numbers given in parenthesis refer to itu line counting. table 46 fine position of hs hdel0 and hdel1 sa 10 (d5 and d4) table 47 output format selection ofts0 and ofts1 sa 10 (d7 and d6); see tables 6 and 7 vrln vref at 60 hz 525 lines vref at 50 hz 625 lines 0 101 length 240 242 286 288 line number ?rst last ?rst last ?rst last ?rst last field 1 (1) 19 (22) 258 (261) 18 (21) 259 (262) 24 309 23 310 field 2 (1) 282 (285) 521 (524) 281 (284) 522 (525) 337 622 336 623 fine position of hs (steps in 2/llc) control bits d5 and d4 hdel1 hdel0 000 101 210 311 v-flag generation in sav/eav-codes control bits d7 and d6 ofts1 ofts0 standard itu 656-format 0 0 v-?ag in sav/eav is generated by vref 0 1 v-?ag in sav/eav is generated by data-type 1 0 reserved 1 1
1999 jul 01 62 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.18 s ubaddress 11h table 48 output control 1 sa 11 function bit logic level data bit colour on (colo) automatic colour killer colo 0 d0 colour forced on colo 1 d0 yuv decoder bypassed (vipb) processed data to vpo output vipb 0 d1 adc data to vpo output; dependent on mode settings vipb 1 d1 output enable real-time (oert) rts0, rts1, rtco high-impedance inputs oert 0 d2 rts0, rtco active, rts1 active, if rtse13 to rtse10 = 0000 oert 1 d2 output enable yuv data (oeyc) vpo-bus high-impedance oeyc 0 d3 output vpo-bus active or controlled by rts1; see table 19 oeyc 1 d3 selection of horizontal lock indicator for rts0, rts1 outputs standard horizontal lock indicator (low-passed) hlsel 0 d4 fast lock indicator (use is recommended only for high performance input signals) hlsel 1 d4 general purpose switch [available on pin rts0, if control byte rtse03 to rtse00 (subaddress 12h) is set to 0010] low gpsw0 0 d5 high gpsw0 1 d5 cm99 compatibility to saa7199 (cm99) default value cm99 0 d6 to be set only if saa7199 (digital encoder) is used for re-encoding in conjunction with rtco cm99 1 d6 general purpose switch [available on pin rts1, if control byte rts103 to rts100 (subaddress 12h) is set to 0010] low gpsw1 0 d7 high gpsw1 1 d7
1999 jul 01 63 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.19 s ubaddress 12h table 49 rts0 output control sa 12 rts0 output control d3 to d0 rtse03 rtse02 rtse01 rtse00 reserved 0000 vipb (subaddress 11h bit 1) = 0: reserved 0001 vipb (subaddress 11h bit 1) = 1: lsbs of the 9-bit adcs gpsw0 level (subaddress 11h, bit 5) 0010 hl (horizontal lock indicator); selectable via hlsel (subaddress 11h, bit 4) 0011 hsel = 0: standard horizontal lock indicator hsel = 1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. vcrs) vl (vertical and horizontal lock) 0100 dl (vertical and horizontal lock and colour detected) 0101 plin (pal/secam sequence; low: pal/dr line is present) 0110 href_hs, horizontal reference signal: indicates valid data on the vpo-bus. the positive slope marks the beginning of a new active line. the pulse width is dependent on the data type selected by the control registers lcr2 to lcr24 (subaddress 41h to 57h; see tables 4 and 61) 0111 data type 0 to 6 8 to 15: high period 1440 llc-cycles (720 samples; see fig.28) data type 7 (upsampled raw data): high period programmable in llc8 steps via hsb7 to hsb0, hss7 to hss0 (subaddress 06h and 07h), fine position adjustment via hdel1 to hdel0 (subaddress 10h, bits 5 and 4) hs, programmable width in llc8 steps via hsb7 to hsb0 and hss7 to hss0 (subaddress 06h and 07h), ?ne position adjustment in llc2 steps via hdel1 to hdel0 (subaddress 10h, bits 5 and 4) 1000 hq (href gated with vref) 1001 odd, ?eld identi?er; high = odd ?eld; see vertical timing diagrams figs 29 and 30 1010 vs (vertical sync; see vertical timing diagrams figs 29 and 30) 1011 v123 (vertical pulse; see vertical timing diagrams figs 29 and 30) 1100 vgate (programmable via vsta8 to vsta0 and vsto8 to vsto0, subaddresses 15h, 16h and 17h) 1101 vref (programmable in two positions via vrln, subaddress 10h, bit 3) 1110 fid (position and polarity programmable via vsta8 to vsta0, subaddresses 15h and 17h and fidp, subaddress 13h bit 3) 1111
1999 jul 01 64 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 50 rts1 output control sa 12 rts1 output control d7 to d4 rtse13 rtse12 rtse11 rtse10 3-state, pin rts1 is used as dot input; see table 19 0000 vipb (subaddress 11h bit 1) = 0: reserved 0001 vipb (subaddress 11h bit 1) = 1: lsbs of the 9-bit adcs gpsw1 0010 hl (horizontal lock indicator); selectable via hlsel (subaddress 11h, bit 4) 0011 hlsel = 0: standard horizontal lock indicator hlsel = 1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e. g. vcrs) vl (vertical and horizontal lock) 0100 dl (vertical and horizontal lock and colour detected) 0101 plin (pal/secam sequence; low: pal/dr line is present) 0110 href_hs, horizontal reference signal: indicates valid data on the vpo-bus. the positive slope marks the beginning of a new active line. the pulse width is dependent on the data type selected by the control registers lcr2 to lcr24 (subaddress 41h to 57h; see tables 4 and 61) 0111 data type 0 to 6, 8 to 15: high period 1440 llc-cycles (720 samples; see fig.28) data type 7 (upsampled raw data): high period programmable in llc8 steps via hsb7 to hsb0, hss7 to hss0 (subaddress 06h and 07h), fine position adjustment via hdel1 to hdel0 (subaddress 10h, bits 5 and 4) hs, programmable width in llc8 steps via hsb7 to hsb0 and hss7 to hss0 (subaddress 06h and 07h), ?ne position adjustment in llc2 steps via hdel1 to hdel0 (subaddress 10h, bits 5 and 4) 1000 hq (href gated with vref) 1001 odd, ?eld identi?er; high = odd ?eld; see vertical timing diagrams figs 29 and 30 1010 vs (vertical sync); see vertical timing diagrams figs 29 and 30 1011 v123 (vertical pulse); see vertical timing diagrams figs 29 and 30 1100 vgate (programmable via vsta8 to vsta0 and vsto8 to vsto0, subaddresses 15h, 16h and 17h) 1101 vref (programmable in two positions via vrln, subaddress 10h, bit 3) 1110 fid (position and polarity programmable via vsta 8 to vsta0, subaddresses 15h and 17h and fidp, subaddress 13 bit 3) 1111
1999 jul 01 65 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.20 s ubaddress 13h table 51 output control sa 13, d7, d4, d3, d1 and d0 note 1. analog-to-digital converter selection via mode3 to mode0 (subaddress 02h; see figs 35 to 38). function bit logic level data bit analog test select (aosl) aout connected to internal test point 1 aosl1 0 d1 aosl0 0 d0 aout connected to input ad1 aosl1 0 d1 aosl0 1 d0 aout connected to input ad2 aosl1 1 d1 aosl0 0 d0 aout connected to internal test point 2 aosl1 1 d1 aosl0 1 d0 field id polarity if selected on rts1 or rts0 outputs if rtse1, rtse0 (subaddress 12h) are set to 1111 default fidp 0 d3 inverted fidp 1 d3 selection bit for status byte functionality oldsb default status information; see table 55 oldsb 0 d4 old status information, for compatibility reasons; see table 55 oldsb 1 d4 analog-to-digital converter output bits on vpo7 to vpo0 in bypass mode (vipb = 1, used for test purposes) adlsb; note 1 ad8 to ad1 (msbs) on vpo7 to vpo0 adlsb 0 d7 ad7 to ad0 (lsbs) on vpo7 to vpo0 adlsb 1 d7
1999 jul 01 66 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 15.2.21 s ubaddress 15h table 52 start of vgate pulse (01-transition) and polarity change of fid pulse field frame line counting decimal value msb (sa 17, d0) control bits d7 to d0 vsta8 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 50hz1st 1 312 1 00111000 2nd 314 1st 2 0... 0 00000000 2nd 315 1st 312 ...310 1 00110111 2nd 625 60hz1st 4 262 1 00000110 2nd 267 1st 5 0... 0 00000000 2nd 268 1st 265 ...260 1 00000101 2nd 3
1999 jul 01 67 philips semiconductors product speci?cation 9-bit video input processor saa7113h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 15.2.22 s ubaddress 16h table 53 stop of vgate pulse (10-transition) field frame line counting decimal value msb (sa 17, d0) control bits d7 to d0 vsto8 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 50hz1st 1 312 1 00111000 2nd 314 1st 2 0... 0 00000000 2nd 315 1st 312 ...310 1 00110111 2nd 625 60hz1st 4 262 1 00000110 2nd 267 1st 5 0... 0 00000000 2nd 268 1st 265 ...260 1 00000101 2nd 3
1999 jul 01 68 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.23 s ubaddress 17h table 54 vgate msbs 15.2.24 s ubaddress 1fh ( read only register ) table 55 status byte video decoder sa 1f 15.2.25 s ubaddress 40h table 56 data slicer clock selection table 57 amplitude searching function logic level control bit vsta8, see sa 15 msb vgate start see table 52 d0 vsto8, see sa 16 msb vgate stop see table 53 d1 i 2 c-bus control bit function data bit rdcap ready for capture (all internal loops locked); active high (oldsb = 0) d0 code colour signal in accordance with selected standard has been detected; active high (oldsb = 1) copro copy protected source detected according to macrovision version up to 7.01 (oldsb = 0) d1 sltca slow time constant active in wipa mode; active high (oldsb = 1) wipa white peak loop is activated; active high d2 glimb gain value for active luminance channel is limited [min (bottom)]; active high d3 glimt gain value for active luminance channel is limited [max (top)]; active high d4 fidt identi?cation bit for detected ?eld frequency; low = 50 hz, high = 60 hz d5 hlvln status bit for horizontal/vertical loop: low = locked, high = unlocked (oldsb = 0) d6 hlck status bit for locked horizontal frequency; low = locked, high = unlocked (oldsb = 1) intl status bit for interlace detection; low = non-interlaced, high = interlaced d7 slicer set (40h) control bits d2 and d1 amplitude searching clksel1 clksel0 reserved 00 13.5 mhz (default) 01 reserved 10 reserved 11 slicer set (40h) control bit d4 amplitude searching hunt_n amplitude searching active (default) 0 amplitude searching stopped 1
1999 jul 01 69 philips semiconductors product speci?cation 9-bit video input processor saa7113h table 58 framing code error table 59 hamming check table 60 field size select slicer set (40h) control bit d5 framing code error fce one framing code error allowed 0 no framing code errors allowed 1 slicer set (40h) control bit d6 hamming check ham_n hamming check for 2 bytes after framing code, dependent on data type (default) 0 no hamming check 1 slicer set (40h) control bit d7 field size select fiset 50 hz ?eld rate 0 60 hz ?eld rate 1
1999 jul 01 70 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.26 s ubaddress 41h to 57h table 61 lcr register 2 to 24 (41h to 57h); see table 4 note 1. the assignment of the upper and lower nibbles to the corresponding field depends on the setting of foff (subaddress 5b, d7); see table 62. table 62 setting of foff lcr register 2 to 24 (41h to 57h) framing code d7 to d4 d3 to d0 dt3 to dt0 (1) dt3 to dt0 (1) wst625 teletext eurowst, ccst 27h 0000 0000 cc625 european closed caption 001 0001 0001 vps video programming service 9951h 0010 0010 wss wide screen signalling bits 1e3c1fh 0011 0011 wst525 us teletext (wst) 27h 0100 0100 cc525 us closed caption (line 21) 001 0101 0101 test line video component signal, vbi region - 0110 0110 intercast oversampled cvbs data - 0111 0111 general text teletext programmable 1000 1000 vitc625 vitc/ebu time codes (europe) programmable 1001 1001 vitc/smpte time codes (usa) programmable 1010 1010 reserved reserved - 1011 1011 nabts us nabts - 1100 1100 japtext moji (japanese) programmable (a7h) 1101 1101 jfs japanese format switch (l20/22) programmable 1110 1110 active video video component signal, active video region (default) - 1111 1111 foff d7 to d4 d3 to d0 0 ?eld 1 ?eld 2 1 ?eld 2 ?eld 1
1999 jul 01 71 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.27 s ubaddress 58h table 63 framing code for programmable data types 15.2.28 s ubaddress 59h table 64 horizontal offset 15.2.29 s ubaddress 5ah table 65 vertical offset 15.2.30 s ubaddress 5bh table 66 field offset, msbs for vertical and horizontal offsets 15.2.31 s ubaddress 5eh table 67 sdid codes slicer set (58h) control bits d7 to d0 programmable framing code fc7 to fc0 (default) 40h slicer set (59h, 5bh) control bits address 5bh, data bits d2 to d0 control bits address 59h, data bits d7 to d0 horizontal offset hoff10 to hoff8 hoff7 to hoff0 recommended value 3h 54h slicer set (5ah, 5bh) control bit 5bh, d4 control bits address 5ah, data bits d7 to d0 vertical offset voff8 voff7 to voff0 minimum value 0 0 0h maximum value 312 1 38h value for 50 hz 625 lines input 0 07h value for 60 hz 525 lines input 0 0ah slicer set (5bh) control bit d7 field offset foff no modi?cation of internal ?eld indicator 0 invert ?eld indicator (even/odd; default) 1 slicer set (5eh) d5 d4 d3 d2 d1 d0 sdid codes sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 sdid5 to sdid0 = 0h (default) 000000
1999 jul 01 72 philips semiconductors product speci?cation 9-bit video input processor saa7113h 15.2.32 s ubaddress 60h ( read - only register ) table 68 slicer status bit (60h) read only table 69 slicer status bit (60h) read only table 70 slicer status bit (60h) read only table 71 slicer status bit (60h) read only note 1. x = dont care. 15.2.33 s ubaddress 61h ( read - only register ) table 72 slicer status bits (61h and 62h) read only 15.2.34 s ubaddress 62h ( read - only register ) table 73 slicer status bits (62h) read only slicer status bit (60h) read only control bit d2 closed caption valid ccv no closed caption in the last frame 0 closed caption detected 1 slicer status bit (60h) read only control bit d3 palplus valid ppv no palplus in the last frame 0 palplus detected 1 slicer status bit (60h) read only control bit d4 vps valid vpsv no vps in the last frame 0 vps detected 1 slicer status bit (60h) read only control bits d6 and d5 framing code valid fc8v fc7v no framing code in the last frame 0 0 framing code with 1 error detected in the last frame 0 1 framing code without errors detected in the last frame 1 x (1) slicer status bits (61h and 62h) read only address 61h, control bits d4 to d0 address 62h, control bits d7 to d4 line number ln8 to ln4 ln3 to ln0 slicer status bits (62h) read only control bits d3 to d0 data type according to table 4 dt3 to dt0
1999 jul 01 73 philips semiconductors product speci?cation 9-bit video input processor saa7113h 16 i 2 c-bus start set-up the given values force the following behaviour of the saa7113h: the analog input ai11 expects a signal in cvbs format; analog anti-alias filter and agc active automatic field detection enabled, pal bdghi or ntsc m standard expected standard itu 656 output format enabled, vbi-data slicer disabled; see table 74 note 2 contrast, brightness and saturation control in accordance with itu standards chrominance processing with nominal bandwidth (800 khz). table 74 i 2 c-bus start set-up values sub (hex) function name (1) values (bin) (hex) 76543210start 00 chip version id07 to id00 read only 01 increment delay x, x, x, x, idel 0 0 0 0 1 0 0 0 08 02 analog input control 1 fuse1 and fuse0, gudl1 to gudl0, mode3 to mode0 11000000 c0 03 analog input control 2 x, hlnrs, vbsl, wpoff, holdg, gafix, gai28 and gai18 00110011 33 04 analog input control 3 gai17 to gai10 0 0 0 0 0 0 0 0 00 05 analog input control 4 gai27 to gai20 0 0 0 0 0 0 0 0 00 06 horizontal sync start hsb7 to hsb0 1 1 1 0 1 0 0 1 e9 07 horizontal sync stop hss7 to hss0 0 0 0 0 1 1 0 1 0d 08 sync control aufd, fsel, foet, htc1, htc0, hpll, vnoi1 and vnoi0 10011000 98 09 luminance control byps, pref, bpss1 and bpss0, vblb, uptcv, aper1 and aper0 00000001 01 0a luminance brightness brig7 to brig0 1 0 0 0 0 0 0 0 80 0b luminance contrast cont7 to cont0 0 1 0 0 0 1 1 1 47 0c chrominance saturation satn7 to satn0 0 1 0 0 0 0 0 0 40 0d chrominance hue control huec7 to huec0 0 0 0 0 0 0 0 0 00 0e chrominance control cdto, cstd2 to cstd0, dccf, fctc, chbw1 and chbw0 00000001 01 0f chrominance gain control acgc, cgain6 to cgain0 0 0 1 0 1 0 1 0 2a 10 format/delay control ofts1 and ofts0, hdel1 and hdel0, vrln, ydel2 to ydel0 00000000 00 11 output control 1 gpsw1, cm99, gpsw0, hlsel, oeyc, oert, vipb and colo 00001100 0c 12 output control 2 rtse13 to rtse10, rtse03 to rtse00 0 0 0 0 0 0 0 1 01 13 output control 3 adlsb, x, x, oldsb, fidp, x, aosl1 and aosl0 00000000 00 14 reserved 0 0 0 0 0 0 0 0 00
1999 jul 01 74 philips semiconductors product speci?cation 9-bit video input processor saa7113h notes 1. all x values must be set to low. for secam decoding set register 0eh to 50h. 2. for proper data slicer programming refer to tables 8 to 11 and 4. 15 vgate start vsta7 to vsta0 0 0 0 0 0 0 0 0 00 16 vgate stop vsto7 to vsto0 0 0 0 0 0 0 0 0 00 17 msbs for vgate control x, x, x, x, x, x, vsto8 and vsta8 0 0 0 0 0 0 0 0 00 18 to 1e reserved 0 0 0 0 0 0 0 0 00 1f decoder status byte intl, hvln, fidt, glimt, glimb, wipa, coprp and rdcap read-only register 20 to 3f reserved 0 0 0 0 0 0 0 0 00 40 slicer control 1 fiset, ham_n, fce and hunt_n 0 0 0 0 0 0 1 0 02 (2) 41 to 57 line control register 2to24 lcrn7 to lcrn0 1 1 1 1 1 1 1 1 ff (2) 58 programmable framing code fc7 to fc0 0 0 0 0 0 0 0 0 00 59 horizontal offset for slicer hoff7 to hoff0 0 1 0 1 0 1 0 0 54 (2) 5a vertical offset for slicer voff7 to voff0 0 0 0 0 0 1 1 1 07 (2) 5b ?eld offset and msbs for horizontal and vertical offset foff, x, x, voff8, x, hoff10 to hoff8 10000011 83 (2) 5c and 5d reserved 0 0 0 0 0 0 0 0 00 5e sliced data identi?cation code x, x, sdid5 to sdid0 0 0 0 0 0 0 0 0 00 5f reserved 0 0 0 0 0 0 0 0 00 60 slicer status byte 1 x, fc8v, fc7v, vpsv, ppv, ccv, x, x read-only register 61 slicer status byte 2 x, x, f21_n, ln8 to ln4 read-only register 62 ln3 to ln0, dt3 to dt0 read-only register sub (hex) function name (1) values (bin) (hex) 76543210start
1999 jul 01 75 philips semiconductors product speci?cation 9-bit video input processor saa7113h 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1999 jul 01 76 philips semiconductors product speci?cation 9-bit video input processor saa7113h 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 jul 01 77 philips semiconductors product speci?cation 9-bit video input processor saa7113h 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 jul 01 78 philips semiconductors product speci?cation 9-bit video input processor saa7113h 19 definitions 20 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 21 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 jul 01 79 philips semiconductors product speci?cation 9-bit video input processor saa7113h notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 66 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 02 67 52 2531, fax. +39 02 67 52 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 545006/01/pp80 date of release: 1999 jul 01 document order number: 9397 750 04567

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